SkillsDrome: All labs

Lab categories:

11. Generate a Ramp output waveform using DAC0800 (Inputs are given to DAC through IC74393 dual 4-bit binary counter).

10. Design and implement an asynchronous counter using decade counter IC to count up from 0 to n (n

b) Design and develop the Verilog / VHDL code for mod-8 up counter. Simulate and verify it’s working.

9. a) Design and implement a mod-n (n

b) Design and develop the Verilog / VHDL code for D Flip-Flop with positive-edge triggering. Simulate and verify it’s working.

8. a) Realize a J-K Master / Slave Flip-Flop using NAND gates and verify its truth table.

7. Design and verify the Truth Table of 3-bit Parity Generator and 4-bit Parity Checker using basic Logic Gates with an even parity bit.

6. a) Design and implement code converter I)Binary to Gray (II) Gray to Binary Code using basic gates.

b) Design and develop the Verilog /VHDL code for an 8:1 multiplexer. Simulate and verify its working.

5. a) Given a 4-variable logic expression, simplify it using Entered Variable Map and realize the simplified logic expression using 8:1 multiplexer IC.

4. Design and implement Half adder, Full Adder, Half Subtractor, Full Subtractor using basic gates.

3. Design and implement an Astable multivibrator circuit using 555 timer for a given frequency and duty cycle.

b) Design and implement a rectangular waveform generator (Op-Amp relaxation oscillator) using a simulation package and demonstrate the change in frequency when all resistor values are doubled.

2. a) Design and construct a rectangular waveform generator (Op-Amp relaxation oscillator) for given frequency and demonstrate its working.

b) Design and implement a Schmitt trigger using Op-Amp using a simulation package for two sets of UTP and LTP values and demonstrate its working.

1. a) Design and construct a Schmitt trigger using Op-Amp for given UTP and LTP values and demonstrate its working.